These tools provide visibility by routing (or “tapping”) signals in your design to debugging logic.
Includes design flow steps, generated file descriptions, and synthesis guidelines.ĭescribes a portfolio of Intel Quartus Prime Pro Edition software in-system design debugging tools for real-time verification of your design.
Includes simulator support, simulation flows, and simulating Intel FPGA IP.ĭescribes support for optional synthesis of your design in third-party synthesis tools by Mentor Graphics and Synopsys.
Define multiple personas for a particular design region without impacting operation in other areas.ĭescribes RTL- and gate-level design simulation support for third-party simulation tools by Aldec*, Cadence*, Mentor Graphics*, and Synopsys* that allow you to verify design behavior before device programming. These advanced flows enable preservation of design blocks (or logic that comprises a hierarchical design instance) within a project, and reuse of design blocks in other projects.ĭescribes Partial Reconfiguration, an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function.
Techniques include optimizing the design netlist, addressing critical chains that limit retiming and timing closure, and optimization of device resource usage.ĭescribes operation of the Intel Quartus Prime Pro Edition software programmer, which allows you to configure Intel FPGAs, and program CPLD and configuration devices via connection with an Intel FPGA Download Cable.ĭescribes block-based design flows, also known as modular or hierarchical design flows. The compiler synthesizes, places, and routes your design before generating a device programming file.ĭescribes the Intel Quartus Prime Pro Edition software settings, tools, and techniques that you can use to achieve the highest design performance in Intel® FPGAs.
Following recommended HDL coding styles ensures that the Intel Quartus Prime Pro Edition software synthesis optimally implements your design in hardware.ĭescribes how to set up, run, and optimize for all stages of the Intel Quartus Prime Pro Edition software compiler. HDL coding styles and synchronous design practices can significantly impact design performance. The Platform Designer automatically generates interconnect logic to connect IP functions and subsystems.ĭescribes best design practices for designing FPGAs with the Intel Quartus Prime Pro Edition software. So now I am just confused.Introduces the basic features, files, and design flow of the Intel Quartus Prime Pro Edition software, including managing Intel Quartus Prime Pro Edition projects and intellectual property (IP), initial design planning considerations, and project migration from previous software versions.ĭescribes how to create and optimize systems using the Platform Designer, a system integration tool that simplifies integrating customized IP cores in your project. And it doesn't quite seem to be associated to the Pin Planner. So which is more correct? It certainly seems like the "External Pin Connection" would be the most accurate, but I cannot seem to find any documentation about when that should be used.
However, there's another option in the Assignment Editor for "Assignment Name": external pin connection. In the Assignment Editor, this shows up as:
In the Pin Planner, I assigned the 50MHz clock, resulting in the following: In my case, I'm using Quartus II 13.1 Web Edition with the DE0-Nano. In a similar vein, I am trying to understand what ends up in the Assignment Editor after a pin assignment.